Dynamic logic uses a sequence of precharge and conditional evaluation phases to realize complex logic functions with less transistors than static logic and shorter delays. During the precharge phase of the clock cycle the output node of a dynamic gate is precharged through a pull-up transistor to V.sub.DD. After precharge, in the evaluation phase, depending upon the values of the inputs a path between the output node and ground may be created. If such a path is created the output node is discharged. If not, the precharged value of the output node is maintained for that cycle.
Domino logic is a dynamic logic family widely used in high speed compact circuits. Domino logic is used in the Pentium Pro.TM. processor, sold by Intel Corp., Santa Clara, Calif.; the Alpha.TM. processor, sold by Compaq Corp., Houston, Tex.; and a variety of other state of the art processors. Clock-delayed ("CD") domino logic is a self-timed dynamic logic family. CD domino logic has a dynamic gate 12 and, if necessary, a clock delay element 14, as shown in FIG. 1. In the most basic clocking scheme, only the clock from the slowest gate at each gate level needs to have a clock delay element. In a more general clocking scheme the clock tree can be designed with each gate using the clock from its slowest input, rather than the same clock for the entire gate level. Using the clock from the slowest input to the gate guarantees that all inputs are stable when a CD domino gate goes into the evaluate phase. The use of a delay element allows CD domino gates to provide a self-timed delay of the precharge/evaluate signal. The precharge evaluate (PE) output of the delay element tells the next gate when the data output is ready. The dynamic gate can be either non-inverting (domino type), as in FIG. 1, or inverting, without an inverter at the output.
The purpose of the delay element 14 is to track the data output. When the PE signal input is low, the dynamic gate will precharge. After the PE signal input switches from low to high, a data input signal has been set up to be evaluated and the dynamic gate drives a final output value onto its output node. CD domino logic is described in more detail in "Clock-Delayed (CD) Domino for Adder and Combinational Logic Design," 1063-6404/96, pp. 332-337, IEEE 1996.
Implementing CD domino logic circuits requires very precise determination of delays, and thorough characterization of the most critical path. A large block containing CD domino logic circuits, such as in a microprocessor, may use six different phase clock signals. Each phase clock signal may be used to control a stage containing a number of operations. For example, a stage may contain 32 operations, and each operation may include two to five gates. All 32 of these operations are performed within the time between the rising edges of two subsequent phase clock signals.
At each stage, it is critical for proper circuit operation that the input signals are valid and stable at each rising clock edge. The clock phase signals can be delayed with respect to the most critical path using fixed delays to attempt to ensure that the input signals are valid and stable at the rising clock edge. However, circuit manufacturing process variations, changes in process parameters, and voltage and temperature variations can all cause changes in the timing of multiple clock phase CD domino logic circuits. To account for all of these variations in the design, explicit margins are considered in the implementation of the clock delay circuits. Improper estimation of these variations may then require hardware modifications to restore valid timing relationships. Thus an improved system of implementing delays in CD domino logic that overcomes these and other problems of the prior art would be highly desirable.
The testing of integrated circuits commonly involves an operation of shifting test instructions and associated test data into an integrated circuit and subsequently analyzing the output generated by the integrated circuit. The Joint Test Access Group (JTAG) developed an integrated circuit and circuit board testing standard called the IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1149.1-1990 and IEEE Std 1149.1a-1993 (referred to herein as the IEEE 1149.1 standard), which is incorporated herein by reference.
The IEEE 1149.1 standard defines test logic that can be included in integrated circuits to provide standardized approaches to testing an integrated circuit, testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board, and observing circuit activity during the circuit's normal operation.
As is well known, a boundary-scan implementation allows for testing of interconnects in a board environment by loading or "scanning in" test patterns into a series of interconnected boundary-scan registers. Each test pattern loaded in the boundary-scan registers provides a different set of control and data signals to the output drivers. The response of the output drivers to the test patterns can be scanned out and captured by an adjacent circuit on the board. To run a functional test vector, an input test pattern is scanned in through the boundary-scan registers. After one or more clock cycles, the response of the circuit can then be captured in the boundary-scan registers and either scanned out or monitored at the output pads.